The acceptance of compiler-developed integrated circuits, often referred to as application specific integrated circuits (ASICs) or standards cells, developed an increased need for improved test techniques for the large variety of circuits produced by those methods. Improved semiconductor manufacturing procedures provided increased complexity semiconductor devices, while compiler design techniques provided a means to rapidly develop designs of many different semiconductor devices. The resulting proliferation of complex ASIC semiconductor devices increased the need for test methods that were flexible, and that could be compiled concurrently with an ASIC design. One technique, generally referred to as built-in self-test (BIST), placed circuitry on the ASIC device to accomplish testing of the ASIC device. BIST may also be utilized to test ASIC devices that include blocks of random access memory (RAM) that is embedded on the ASIC device.
There are essentially three elements associated with the BIST function: 1) the BIST controller, 2) the data generator, and 3) the data analyzer. The BIST controller provides synchronization and control signals for the BIST operation. The data generator provides a stimulus to the circuit (ASIC) under test. Finally, the data analyzer provides a mechanism for compacting the response from the circuit under test to form a result. Further, the BIST includes an address generator when the device under test is a memory device such as a RAM.
A data analyzer analyzes the output of the device under test. One type of analysis that the data analyzer performs is called comparison analysis wherein an actual output stream from the device under test is compared with an expected result data stream. Whenever a difference between the two data streams occurs, an error has occurred. However, typically the BIST circuit continues to test the device under test and the location of the fault that triggered the error is later investigated. However, it would be advantageous to be able to stop the Operation of the BIST when an error has occurred in order to more quickly determine where the error has occurred and, thus, locate the fault.
Moreover, as mentioned above, the BIST circuitry includes an address generator as well as a data generator when the device under test includes a memory device such as a RAM. Further, it would be advantageous to utilize the already existing BIST circuitry to provide access to a memory device even when the BIST circuitry is not testing the memory device. For example, one may wish to read or write to a RAM when performing various testing at bench.
Hence, there exists a need to provide an improved BIST circuit which has the capability of halting the testing of a device under test when an error has occurred. Moreover, there exists a need to utilize the BIST circuitry already present to provide access to a storage device for other reasons than conventional BIST testing.